The invention relates to a frequency converter comprising:
a frequency divider intended to receive an input signal having a so-called input frequency, and to supply an output signal having a so-called output frequency, and
an input port intended to receive a control word determining a division ratio between the input and output frequencies of the frequency divider.
Such frequency converters are commonly employed in phase-locked loops intended to adjust and regulate a so-called oscillation frequency of an output signal of an oscillator. Such a phase-locked loop is described in European patent application EP 0 821 488 A1. In most of the known phase-locked loops, the frequency divider receives the output signal from the oscillator and supplies, to a phase/frequency comparator, an output signal having a frequency that is N times lower than the oscillation frequency, N being an integer equal to that of the control word. The phase/frequency comparator compares this frequency with a so-called comparison frequency of a reference signal originating, for example, from a quartz oscillator. If the output frequency of the frequency divider is below the comparison frequency, the phase/frequency comparator commands an increase of the oscillation frequency until the oscillation frequency is equal to N times the comparison frequency. Since the comparison frequency is fixed, the choice of the value of N of the control word determines the value of the oscillation frequency. Consequently, the minimum interval between two oscillation frequency values is equal to the value of the comparison frequency. It has been found that the performance in terms of noise of a phase-locked loop is better as the comparison frequency is higher. However, choosing a high comparison frequency means an increase of the minimum interval between two values of the oscillation frequency, which interval is determined by the conditions wherein the phase-locked loop is employed. Thus, in applications where the output signal of the oscillator is used to receive hertzian digital television signals, this minimum interval is predetermined and set at 166.67 kHz.
To maintain a constant minimum interval while increasing the value of the comparison frequency, it is thus necessary to use a frequency divider whose division ratio has a non-integer value. Such frequency dividers are commonly referred to asxe2x80x9cfractional-Nxe2x80x9d frequency dividers. Their division ratio is determined by at least two parameters.
A user who would like to replace a frequency divider whose division ratio is an integer by a fractional-N type divider in order to improve the noise performance of a phase-locked loop while using a higher comparison frequency, must, in principle, supply two, instead of one, control words to the frequency divider, which will require the user to make substantial and expensive modifications in the phase-locked loop as designed by the user in the known model.
It is an object of the invention to overcome this drawback by proposing a frequency converter intended to replace the frequency dividers present inside the known phase-locked loops, which frequency converter can be programmed by the user by means of a unique control word, although the phase-locked loop thus obtained can use a comparison frequency that is higher than that in the known phase-locked loop, thus enabling a better noise performance to be achieved without modifying the minimum interval between two oscillation frequencies.
Indeed, in accordance with the invention, a frequency converter as described in the opening paragraph additionally includes interface means arranged between the input port and the frequency divider, and intended to carry out a conversion of a value of the control word into a first and a second parameter defining a non-integer value of the division ratio of the frequency divider.
By virtue of the invention, the two parameters necessary to define a non-integer division ratio of the frequency divider are extracted within the frequency converter, in a manner that is perfectly transparent to the user, on the basis of the value N of the control word elaborated by the user to program a known phase-locked loop using a frequency divider having an integer division ratio.
For a large number of known fractional-N type dividers, the division ratio R can be expressed by the formula R=M+k/q, where M and k are the first and the second parameter, q being a third integer parameter whose value is predetermined by the value of the minimum interval between two oscillation frequencies, which is to be kept constant. Thus, q=FCOMP/FSTEP, where FCOMP is the chosen comparison frequency and FSTEP is the minimum interval. In such a case, the interface means included in the frequency converter in accordance with the invention advantageously comprise:
means for computing the integer part of the ratio N/q, between the value of the control N and that of the third parmameter q, which integer part constitutes the first parameter M, and
means for computing the difference Nxe2x88x92M.q between the value of the control word and the value of the product of the first and third parameters, which difference constitutes the second parameter k.
In such an embodiment of the invention, the first parameter is formed by the quotient of the division of the value N of the control word by the value of the third parameter q, while the second parameter k is formed by the remainder of such a division.
In a particularly advantageous embodiment of the invention, if the third parameter is coded on P bits, the interface means contain:
a shift register intended to receive the control word, coded on L bits, of which the P most significant bits may be subjected to a parallel loading operation,
a P bit adder intended to receive at an input the P most significant bits of the shift register, and to receive, at another input, the two""s complement of the third parameter, and
a sequencer intended to clock Lxe2x88x92P computing steps, each computing step including the following operations:
adding the values present at the inputs of the adder,
loading the P least significant bits of the result of the addition to the P most significant bits of the shift register, if the result is positive,
loading, into a storage flip-flop next to the least significant bit of the shift register, a carry bit produced by the adder, and
shifting the content of the shift register in the direction of the most significant bits, the value of the least significant bit of this register becoming the value of the carry bit.
As stated hereinabove, a frequency converter in accordance with the invention will be advantageously employed in a phase-locked loop intended to regulate the frequency of an oscillator, as it enables the noise performance of such a loop to be improved in a manner that is transparent to a user accustomed to the known phase-locked loops. Therefore, the invention also relates to a phase-locked loop comprising:
an oscillator intended to produce an output signal having an oscillation frequency whose value depends on the value of a tuning signal,
a phase/frequency detector intended to compare the oscillation frequency with a so-called comparison frequency of a reference signal, and to supply the tuning signal to the oscillator, the value of said tuning signal depending on the result of the comparison, and
a frequency divider described hereinbefore, which is arranged between the oscillator and the phase/frequency detector.
In an embodiment of such phase-locked loops, the invention finally relates to a device intended to receive radioelectric signals, for example a television receiver or a radiotelephone, comprising:
an input stage system intended to receive a radioelectric signal and to convert said signal to an electronic output signal having a so-called radio frequency,
an oscillator intended to supply an output signal having a so-called oscillation frequency, and
a mixer intended to receive the output signals from the input stage and the oscillator, and to supply a signal whose frequency is equal to the difference between the radio frequency and the oscillation frequency,
which device is characterized in that it comprises, in addition, a phase-locked loop as described hereinabove, which is intended to adjust the value of the oscillation frequency.
These and other aspects of the invention will be apparent from and elucidated with reference to the non-limitative exemplary embodiment(s) described hereinafter.